تصميم بنية هجينة لتنفيذ خوارزمية AES على FPGA لتطبيقات إنترنت الأشياء
DOI:
https://doi.org/10.21123/bsj.2024.8931الكلمات المفتاحية:
خوارزمية AES، التشفير/ فك التشفير، غرض الشيء، FPGA، VHDL، الأمان.الملخص
تتطلب خوارزميات التشفير عالية الأمان مثل AES قدرات حسابية عالية لتحقيق أمن المعلومات. لذلك، من الضروري استخدام بنيات الحوسبة المتوازية التي تستغل التقنيات الحديثة في التوازيات المكانية للحصول على أكبر قدر من القوة الحسابية التي يمكن تصورها. تم إدخال تقنيات مختلفة لتحقيق المعالجة المتوازية. إحداها هي مصفوفات البوابات القابلة للبرمجة ميدانيًا (FPGAs)، والتي تتميز بخصائص جيدة مناسبة لتنفيذ بنيات متوازية مع استهلاك أقل للطاقة. تهدف الورقة إلى تصميم وتنفيذ جهاز إرسال واستقبال مدمج لبنية محرك المعالجة الحاسوبية ذو أداء عالٍ للحصول على إنتاجية أفضل على تقنية FPGA لتشفير وفك تشفير الصور. في هذا التصميم، تم استخدام لوحتين، "DE1_Soc و NEEK board" مع جهاز Altera Quartus prime 18.1، وجهاز cyclone V 5CSEMA5F31C6 FPGA للتوليف والمحاكاة. أظهرت نتائج التنفيذ أن البنية المقترحة تتمتع بكفاءة الأداء من حيث تردد التشغيل 600 ميكا هرتز والإنتاجية 76.8 كيكا هرتز.
Received 13/04/2023
Revised 28/05/2024
Accepted 30/05/2024
Published Online First 20/11/2024
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الحقوق الفكرية (c) 2024 Nada Qasim Mohammed , Amiza Amir , Muataz Hammed Salih , R. Badlishah Ahmad , Rima Matem , Nisrean Thalji , Qasim Mohammed , Jamal Kamil K. Abbas, Taha Raad Al-Shakhli
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