Design Hybrid Architecture to Implement AES Algorithm on FPGA for IoT Applications

Authors

  • Nada Qasim Mohammed Faculty of Electronic Engineering Technology, University Malaysia Perlis, 02600 Arau, Malaysia.
  • Amiza Amir Faculty of Electronic Engineering Technology, University Malaysia Perlis, 02600 Arau, Malaysia.
  • Muataz Hammed Salih Automation Group, Design and Engineering, Flex, Penang, 11500, Malaysia.
  • R. Badlishah Ahmad Faculty of Electronic Engineering Technology, University Malaysia Perlis, 02600 Arau, Malaysia.
  • Rima Matem Faculty of Electronic Engineering Technology, University Malaysia Perlis, 02600 Arau, Malaysia.
  • Nisrean Thalji Department of Robotics and Artificial Intelligence, Jadara University, Irbid, Jordan.
  • Qasim Mohammed Department of Cybersecurity Science, Al-Kunooz University College, Basrah, Iraq.
  • Jamal Kamil K. Abbas Cybersecurity Engineering Techniques, Al-Nisour University College, Baghdad, 10036, Iraq. https://orcid.org/0000-0002-5102-9538
  • Taha Raad Al-Shakhli Cybersecurity Engineering Techniques, Al-Nisour University College, Baghdad, 10036, Iraq.

DOI:

https://doi.org/10.21123/bsj.2024.8931

Keywords:

AES algorithm, Encryption /Decryption, Intent of thing, FPGA, VHDL, Security.

Abstract

High-security cryptography algorithms like AES require high computational capabilities to achieve information security.  Therefore, it is necessary to use parallel computing architectures that exploit modern technologies in spatial parallelisms to obtain the most conceivable computational power. Various technologies have been introduced to achieve parallel processing. One of them is field-programmable gate arrays (FPGAs), which have good characteristics suitable for implementing parallel architectures with lower power consumption. The paper aims to design and implement an embedded computing processing engine architecture transceiver with high performance to obtain better throughput on FPGA technology to encrypt and decrypt images. In this design, two boards are used, "DE1_Soc and NEEK board" with Altera Quartus prime 18.1, cyclone V 5CSEMA5F31C6 FPGA device for synthesis and simulation. The implementation results show that the proposed architecture has an efficient performance in terms of an operating frequency is 600 MHZ and a throughput is 76.8 GHZ.

Received 13/04/2023

Revised 28/05/2024

Accepted 30/05/2024

Published Online First 20/11/2024

References

Jabir H, Fanfakh A. An Overview of Parallel Symmetric Cipher of Messages. J Univ Babylon Pure Appl Sci. 2023 Jun 30; 31(2): 19 -33. https://doi.org/10.29196/jubpas.v31i2.4652.

Rajasekar P, Mangalam H, Kumar CS. Logic Realization of Galois Field for AES SBOX using Quantum Dot Cellular Automata. J Supercomputing 2023 Feb; 79(3): 3024-3054. ‏ https://doi.org/10.1108/CW-04-2019-0039.

Qassir SA, Gaata MT, Sadiq AT. Modern and Lightweight Component-based Symmetric Cipher Algorithms. Aro Sci J Koya Univ. 2022; 10(2): 152-168. http://dx.doi.org/10.14500/aro.11007.

Phadikar A, Mandal H, Chiu TL. Parallel hardware implementation of data hiding scheme for quality access control of grayscale image based on FPGA. Multidimens Syst Signal Process. 2020 Jan; 31:73-101. https://doi.org/10.1007/s11045-019-00650-x

Mohammed NQ, Hussein QM, Sana AM, Khalil LA. A Hybrid Approach to Design Key Generator of Cryptosystem. J Comput Theor Nanosci. 2019 Mar 1; 16(3): 971-977. https://doi.org/10.1166/jctn.2019.7985.

Nabil M, Khalaf AA, Hassan SM. Design and implementation of pipelined and parallel AES encryption systems using FPGA. Indonesian J Electr Eng Comput Sci. 2020 Oct; 20(1): 287-299. http://doi.org/10.11591/ijeecs.v20.i1.pp287-299‏

Hameed ME, Ibrahim MM, Abd Manap N. Review on improvement of advanced encryption standard (AES) algorithm based on time execution, differential cryptanalysis and level of security. J Telecommun Electron Comput Eng. 2018 Jan 15; 10(1): 139-145.

Mane PB, Mulani AO. High speed area efficient FPGA implementation of AES algorithm. Int J Reconfigurable Embed Syst. 2018 Nov; 7(3): 157-165. https://doi.org/10.11591/ijres.v7.i3.pp157-165

Noorbasha F, Cheruvu JH, Boina P, Battineni SV. Design of AES based cipher and decipher cryptography system using Verilog HDL. J Phys.: Conf Series. IOP Pub., 1804 (2021): 012170. https://doi.org/10.1088/1742-6596/1804/1/012170.

Mohammed NQ, Amir A, Salih MH, Arrfou H, Mohammed Q. Implementation Dual Parallelism Cybersecurity Architecture on FPGA. J Commun. 2022 May; 17(5): 396-402. https://doi.org/10.12720/jcm.17.5.386-392

Mohammed NQ, et al. A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform. 2023 IEEE Int Conf Adv Sys Emrg Tech. (IC_ASET) 2023 Apr 29 (pp. 1-6). IEEE. https:doi.org/ 10.1109/IC_ASET58101.2023.10150938

Shahid Mustafizur Rahman. Deep learning for Internet of Things (IoT) network security. 2021. PhD Thesis. Inst. Polytechnique de Paris.‏

Rupani A, Sujediya G. A Review of FPGA implementation of Internet of Things Int J Innovative Res Comp Comm Eng. 2016 Sep; 4(9): 16203-16207. ‏

Rose K, Eldridge S, Chapin L. The internet of things: An overview. I Soc. 2015 Oct 15; 80: 1-50.

Burhan M, Rehman RA, Khan B, Kim BS. IoT elements, layered architectures and security issues: A comprehensive survey. sensors. 2018 Aug 24; 18(9): 2796-2832. https://doi.org/10.3390/s18092796.

Marafa FM, Sa’ad S, Tukur A, Mohammed A. A Review on Impact of Internet of Things (IoT) on Individual Privacy in Smart Home Systems. 2021 2nd Int Conf Intel Eng Manag. 2021 Apr 28 (pp. 127-131). IEEE. https://doi.org/10.1109/ICIEM51511.2021.9445330

Elkhodr M, Shahrestani S, Cheung H. The internet of things: New interoperability, management and security challenges. arXiv preprint arXiv: 1604.04824. 2016 Apr 17;8(2):85-102 http://dx.doi.org/10.5121/ijnsa.2016.8206

Shaukat K, Alam TM, Hameed IA, Khan WA, Abbas N, Luo S. A review on security challenges in internet of things (IoT). 26th IEEE International Conference on Automation and Computing 26th Int conf automation and comp. (ICAC). 2021 Sep 2 (pp. 1-6). IEEE. https://doi.org/10.23919/ICAC50006.2021.9594183.

Hussien QM, Habeeba FA. Survey on data security techniques in internet of things. Al-Kunooze Sci J. 2021; 2(2):27-37.

Karimian GH, Rashidi B. A high speed and low power image encryption with 128-bit AES algorithm. Int J Electr Comput Eng.. 2012 Jun 1; 4(3): 367- 372 .https://doi.org/10.7763/IJCEE.2012.V4.514.

Mohammed NQ, Salih MH, Aliana R, Hussein QM, Khalid NA. Design and implementation image processing functional unit using spatial parallelism on FPGA. ARPN J Eng Appl Sci. 2018; 13(15): 4514-4520.

Gore M, Deotare V. FPGA Implementation of Area Optimized AES for Image Encryption/Decryption Process. I J N G C A. 2013; 1(9): 23-26. https://doi.org/10.1109/ICCSP.2015.7322746.

Rahimunnisa K, Karthigaikumar P, Rasheed S, Jayakumar J, SureshKumar S. FPGA implementation of AES algorithm for high throughput using folded parallel architecture. Secur Commun Netw. 2014 Nov; 7(11): 2225-2236. https:doi.org/1002/sec.651

AL-ODAT Zeyad, Mazhar Ali, Assad Abbas, Samme Ullah. Secure hash algorithms and the corresponding FPGA optimization techniques. ACM Comput Surv. 2020; 53(5): 1-36.‏ https://doi.org/10.1145/3311724.

Jumaa NK. Survey: internet of thing using FPGA. Iraqi J Electr Electron EngJ. 2017; 13(1): 38-45. https://doi.org/10.33762/eeej.2017.128785.

Tausif M, Ferzund J, Jabbar S, Shahzadi R. Towards Designing Efficient Lightweight Ciphers for Internet of Things. KSII Trans Internet Inf Syst. 2017 Aug 1; 11(8):1-10. https://doi.org/10.3837/tiis.2017.08.014

Willam S. Cryptography and Network Security: Principles and Practice (Global Edition-). Pearson Education; 2022. http://elib.vku.udn.vn/handle/123456789/2881

Zodpe H, Sapkal A. An efficient AES implementation using FPGA with enhanced security features. J King Saud Univ Eng. Sci. 2020 Feb 1; 32(2): 115-122. https://doi.org/10.48550/arXiv.2101.01177.

Kamalakkannan K, Mudalige GR, Reguly IZ, Fahmy SA. High-level FPGA accelerator design for structured-mesh-based explicit numerical solvers. 35th IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2021 May 17 (pp. 1087-1096). ‏ https://doi.org/10.48550/arXiv.2101.01177.

Vaigandla KK, Karne R, Siluveru M, Kesoju M. Review on Blockchain Technology: Architecture, Characteristics, Benefits, Algorithms, Challenges and Applications. Mesopotamian J Cyber Security. 2023 Mar 24; 2023: 73-85. https://doi.org/10.58496/MJCS/2023/012.

Al-Amri RM, Hamood DN, Farhan AK. Theoretical Background of Cryptography. Mesopotamian J. Cyber Security. 2023 Jan 26; 2023: 7-15. https://doi.org/10.58496/MJCS/2023/002.

Rimani R, Naima HA, Pacha AA, Ramos JA. An Efficient Image Encryption Using a Dynamic, Nonlinear and Secret Diffusion Scheme. Baghdad Sci J. 2021 Sep 1; 18(3): 628-639. https://doi.org/10.21123/bsj.2021.18.3.0628.

Khudhair ZN, Nidhal A, El Abbadi NK. Text multilevel encryption using new key exchange protocol. Baghdad Sci J. 2022 Jun 1; 19(3): 619-630. ‏ https://doi.org/10.21123/bsj.2023.7315.

Abdul-Ghani SA, Abdul-Wahhab RD, Abood EW. Securing text messages using graph theory and steganography. Baghdad Sci J. 2022 Feb 1; 19(1): 0189-. ‏ https://doi.org/10.21123/bsj.2022.19.1.0189.

Salim KG, Al-alak SM, Jawad MJ. Improved image security in internet of thing (IoT) using multiple key AES. Baghdad Sci J. 2021 Jun 1; 18(2): 417-429 https://doi.org/10.21123/bsj.2021.18.2.0417

Arul Murugan C, Karthigaikumar P, Sathya Priya S. FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications. Automatika. 2020 Oct 1; 61(4): 682-693. https://doi.org/10.1080/00051144.2020.1816388.

Farooq U, Aslam MF. Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA. J King Saud Univ. Comput Inf Sci. 2017 Jul 1; 29(3): 295-302. https://doi.org/10.1016/j.jksuci.2016.01.004

Wong DS, Tabereaux A, Lavoie P. Anode effect phenomena during conventional AEs, low voltage propagating AEs & non-propagating AEs. L Met. 2014. 2016: 529-534. https://doi.org/10.1002/9781118888438.ch90

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Copyright (c) 2024 Nada Qasim Mohammed , Amiza Amir , Muataz Hammed Salih , R. Badlishah Ahmad , Rima Matem , Nisrean Thalji , Qasim Mohammed , Jamal Kamil K. Abbas, Taha Raad Al-Shakhli

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Design Hybrid Architecture to Implement AES Algorithm on FPGA for IoT Applications. Baghdad Sci.J [Internet]. [cited 2024 Dec. 23];22(6). Available from: https://bsj.uobaghdad.edu.iq/index.php/BSJ/article/view/8931
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